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Deuterium annealing has been widely used to help improve hot carrier injection (HCI) reliability of CMOS devices[1]. With introduction of high-k, and especially the gate-last metal gate processes, which decouples the high temperature annealing process, the effectiveness of D2 anneal is further investigated in this report. Especially, 20nm gate-last high-k/metal gate planar transistor was characterized in terms of threshold, gate leakage, charge pumping current, and reliability with and without D2 anneal and show that D2 anneal is very effective in suppressing HCI by up to ~3x. We also show that D2 anneal continues to be effective in 14nm 3-D FinFET transistors. The gate length used in this experiment is 20nm and the width is 1um for the 20nm node gate-last planar transistors. For annealing, pure deuterium gas (D2) is applied to all samples at The passivation rate k2 for between Si and D2 reaction and Vth can be expressed by eq. (1) and (2). As the deuterium pressure goes up, the passivation rate also increases and as a result, the interface trap density (Dit) reduces. Interface trap generation induced substrate current (ICP) was measured by the charge pumping technique in Fig. 1. Process applying the highest annealing pressure results in the lowest ICP. In other words, it explicitly explains that higher D2 pressure had higher D2 absorption rate at the Si/SiO2 interfaces as expressed in eq. (1). Specially in eq. (2), Qit is dependent on the surface potential, which is dependent on the gate voltage. As a result, the decrease in Qit causes successive threshold voltage increase as shown in Fig. 2. PMOS had higher sensitivity to Qit as its performance and reliability characteristics heavily rely on the IL-interface, whereas, NMOS depends more on the high-k region[3]. In addition, Qot, which is a cause for gate leakage current in off-state, can be suppressed through the diffusion of deuterium after annealing. Off-leakage current at subthreshold region decreases by more than 30% both in annealed P/NMOS devices in our experiment. Deuterium annealing process can improves not only device performance but also reliability. Fig. 3 shows HCI and BTI reliability versus stress time respectively. Fig. 3 represents that D2 annealing process improves hot carrier reliability by up to ~3x at 5000sec stress time for PMOS and ~2x for NMOS. Comparing with conventional hydrogen annealing process, deuterium has bigger mass and approximately 100 times slower desorption rate than hydrogen from the silicon[4], so D2 annealing process had less Vth change was anticipated. But, un-optimized additional annealing could also detach the deuterium from the silicon interface, that can cause increase in the number of dangling bonds in silicon interface. As shown in Fig. 3, there is a big improvement in HCI reliability, whereas, there are no significant differences in BTI reliability. These phenomenon is expected by deuterium desorption mainly due to the channel hot carriers. The channel hot carriers results in the reappearance of the interface defects, and degradation during HCI. Threshold voltage shift as a function of various BTI stress temperature with high pressure annealed wafer was extracted, and thermal activation energy of ~0.2eV was found from the temperature dependence in 20nm gate-last high-k/metal gate CMOS device. Fig. 4 shows the charge pumping result in 14nm FinFET devices. Comparison of ICP between 1x anneal (after M1 process) and 2x anneals (M1, and Final Metal) is shown. There is very small incremental change with 1x D2 anneals at the final metal layer. It means that D2 diffusion process is not the rate-limiting step, and the number of D2 annealing time is negligible in 3-D FinFET devices. We also verify hot carrier impact on the devices with different oxide thickness. More degradation is found in EG than SG as shown in Table 1. It is expected that higher voltage stress during HCI can easily detach the deuterium near Si interfaces in EG than SG, it causes more Vth shift degradation in EG. In conclusion, deuterium incorporation has improved HCI by 2x while achieving higher performance in 20nm gate-last high-k/metal gate technology. The effect of D2 anneal is highly expected to be continued in 14nm 3-D FinFET device. In the near future, D2 impacts using various split conditions on 14nm 3-D devices will be more deeply studied. References Kangguo Cheng, et al., Microelectronic engineering 56, pp353-358, 2001 Ki-Dan Bae, et al., ECS transaction 58 (70), pp3-7, 2013 Sangwoo Pae et al., IRPS, pp352-357, 2008 Jae-Sung Lee, Transactions on electrical and electronic materials, vol. 13, No. 4, pp188-191, August 25, 2012 Figure 1 |
