Architecture for hardware driven image inspection based on FPGAs
| Autor: | Johannes Fürtler, Christian Eckel, Konrad Mayer, Jörg Brodersen, Peter Rossler, Herbert Nachtnebel, Gerhard Cadek |
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| Rok vydání: | 2006 |
| Předmět: |
Digital signal processor
business.industry Data parallelism Computer science Distortion (optics) Image processing law.invention Lens (optics) law Distortion Digital image processing Computer data storage Scalability System on a chip Pyramid (image processing) business Field-programmable gate array Computer hardware |
| Zdroj: | Real-Time Image Processing |
| ISSN: | 0277-786X |
| DOI: | 10.1117/12.642797 |
| Popis: | Requirements for contemporary print inspection systems for industrial applications include, among others, high throughput, examination of fine details of the print, and inspection from various perspectives and different spectral sensitivity. Therefore, an optical inspection system for such tasks has to be equipped with several high-speed/high-resolution cameras, each acquiring hundreds of megabytes of data per second. This paper presents an inspection system which meets the given requirements by exploiting data parallelism and algorithmic parallelism. This is achieved by using complex field-programmable gate arrays (FPGA) for image processing. The scalable system consists of several processing modules, each representing a pair of a FPGA and a digital signal processor. The main chapters of the paper focus on the functionality implemented in the FPGA. The image processing algorithms include flat-field correction, lens distortion correction, image pyramid generation, neighborhood operations, a programmable arithmetic unit, and a geometry unit. Due to shortage of on-chip memory, a multi-port memory concept for buffering streams of data between off-chip and on-chip memories is used. Furthermore, performance measurements of the processing module are presented. |
| Databáze: | OpenAIRE |
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