An FPGA-Based Hardware Emulator for Neuromorphic Chip With RRAM
| Autor: | Chuping Qu, Xuan Wang, Tao Luo, Wai Teng Tang, Rick Siow Mong Goh, Matthew Lee, Weng-Fai Wong |
|---|---|
| Rok vydání: | 2020 |
| Předmět: |
Spiking neural network
Emulation Artificial neural network business.industry Computer science Hardware_PERFORMANCEANDRELIABILITY 02 engineering and technology Integrated circuit design Memristor Chip Computer Graphics and Computer-Aided Design 020202 computer hardware & architecture Resistive random-access memory law.invention Neuromorphic engineering Gate array law Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Electrical and Electronic Engineering Crossbar switch business Field-programmable gate array Software Computer hardware |
| Zdroj: | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 39:438-450 |
| ISSN: | 1937-4151 0278-0070 |
| Popis: | Neuromorphic chip with RRAM devices has been demonstrated as a promising computing platform for neural network-based applications. By directly mapping the weight matrices of neural networks onto RRAM-based crossbar arrays, high energy, and area efficiency can be achieved. However, the design of an RRAM-based neuromorphic chip faces many constraints due to the variability and limitations of RRAM. Simulation and emulation can help in the design of a neuromorphic chip prior to fabrication. However, software-based chip simulation on CPU is slow, especially for large-scale network-on-chip (NoC)-based chip design. In this paper, we present a hardware emulator on field-programmable gate array (FPGA) for an RRAM-based neuromorphic chip. Our emulator supports the emulation of static and dynamic variation of the RRAM-based crossbars used in the neural cores of a neuromorphic chip. Furthermore, an NoC is also implemented on FPGA to emulate the communication between the neural cores. Using the emulator, we show that effects, such as RRAM write and read noise and stuck-at faults affect the accuracy of an application on a neuromorphic chip. We also demonstrate the utility of the emulator in investigating NoC topologies, routing buffer depths, and neural core mappings. |
| Databáze: | OpenAIRE |
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