A Layout Structure for Matching Many Integrated Resistors
| Autor: | G.G. Chu, C.L. Conrad, J.P.A. van der Wagt |
|---|---|
| Rok vydání: | 2004 |
| Předmět: |
Very-large-scale integration
Engineering Physics::Instrumentation and Detectors business.industry Electrical engineering Mixed-signal integrated circuit Integrated circuit layout Circuit extraction Computer Science::Other law.invention Computer Science::Emerging Technologies Design layout record law Electronic engineering Electrical and Electronic Engineering Resistor Physical design business IC layout editor |
| Zdroj: | IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications. 51:186-190 |
| ISSN: | 1057-7122 |
| DOI: | 10.1109/tcsi.2003.821303 |
| Popis: | A proposed mirrored shuffle layout pattern cancels systematic resistor gradient variations up to second order and allows monolithic integration of hundreds of matched resistors for precision analog circuits. A test circuit uses 15 000 subresistors and three levels of interconnect to form 150 main resistors in a 2.85/spl times/0.83 mm/sup 2/ area. It demonstrates better than 11-b matching. The dominant remaining error is related to a layout artifact external to the core resistor array, and after separation the resistor array itself achieves over 13-b matching. Wafer maps show significant first- and second-order resistor value gradients that are cancelled to within the measurement error. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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