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H.264 video compression algorithm was introduced by ITU-T to improve the quality at the cost of increased computational complexity. The spatial redundancy of the video frames in H.264 is minimized using intra prediction tool. In this paper the low power of intra prediction architecture is proposed to reduce number of computations and improve the speed. Memory segmentation is used to select the mode in intra prediction to optimize the power. The results are tested for Akiyo, Foreman and Grandma video frames. Power reduction of 18% is obtained using system level simulation. The proposed algorithm is implemented in Verilog HDL. The code is verified for test video sequences in base line profile QCIF format with 176*144 resolutions. Using data correlation , the number of computations is minimized by 21% for frame with high texture like Akiyo that improves the speed. |
