An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches
| Autor: | Damir Jamsek, Robert K. Montoye, Leland Chang, Kevin A. Batson, Wilfried Haensch, Richard J. Eickemeyer, Yutaka Nakamura, Robert H. Dennard |
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| Rok vydání: | 2008 |
| Předmět: |
Engineering
Hardware_MEMORYSTRUCTURES Tolerance analysis business.industry CPU cache Hardware_PERFORMANCEANDRELIABILITY Integrated circuit law.invention CMOS law Power electronics Dynamic demand Electronic engineering Static random-access memory Electrical and Electronic Engineering business Low voltage |
| Zdroj: | IEEE Journal of Solid-State Circuits. 43:956-963 |
| ISSN: | 0018-9200 |
| DOI: | 10.1109/jssc.2007.917509 |
| Popis: | An eight-transistor (8T) cell is proposed to improve variability tolerance and low-voltage operation in high-speed SRAM caches. While the cell itself can be designed for exceptional stability and write margins, array-level implications must also be considered to achieve a viable memory solution. These constraints can be addressed by modifying traditional 6T-SRAM techniques and conceding some design complexity and area penalties. Altogether, 8T-SRAM can be designed without significant area penalty over 6T-SRAM while providing substantially improved variability tolerance and low-voltage operation with no need for secondary or dynamic power supplies. The proposed 8T solution is demonstrated in a high-performance 32 kb subarray designed in 65 nm PD-SOI CMOS that operates at 5.3 GHz at 1.2 V and 295 MHz at 0.41 V. |
| Databáze: | OpenAIRE |
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