| Autor: |
Jun Ohtani, Tomoya Kawagoe, M. Niiro, M. Maruta, Tsukasa Ooishi, Hideto Hidaka |
| Rok vydání: |
2002 |
| Předmět: |
|
| Zdroj: |
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169). |
| DOI: |
10.1109/cicc.2001.929752 |
| Popis: |
A shared built-in self-repair analysis scheme (Shared-BISA) for multiple embedded memory cores in the SOC is proposed to realize minimum area penalty independent of the number of embedded memory cores. A compact reconfigurable CAM array in the BISA circuitry realizes a flexible redundancy analysis structure to cope with various memory core and redundancy structures, and a high-speed operation up to 500 MHz. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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