An 8.5-ns 112-b transmission gate adder with a conflict-free bypass circuit
| Autor: | H. Okada, T. Sato, G. Goto, T. Sukemura, M. Sakate |
|---|---|
| Rok vydání: | 1992 |
| Předmět: |
Adder
Signal generator Floating point business.industry Computer science Circuit design Transistor Electrical engineering Hardware_PERFORMANCEANDRELIABILITY Propagation delay Integrated circuit law.invention Transmission gate CMOS law Hardware_INTEGRATEDCIRCUITS Serial binary adder Carry-save adder Hardware_ARITHMETICANDLOGICSTRUCTURES Electrical and Electronic Engineering Cmos process business Hardware_LOGICDESIGN Electronic circuit |
| Zdroj: | IEEE Journal of Solid-State Circuits. 27:657-659 |
| ISSN: | 0018-9200 |
| DOI: | 10.1109/4.126557 |
| Popis: | The authors discuss the weak point of a conventional bypass circuit, or carry-skip paths in a Manchester adder, and propose a new bypass circuit and its control scheme to avoid transitory fighting that causes an intermediate voltage. A 112-b transmission gate adder is presented. It uses a group of three mutually exclusive transmission gates for the carry-skip paths and a new conditional sum generation circuit. It has an estimated propagation delay time of 8.5 ns and 6941 transistors, both of which are smaller than for conventional carry select adders. The adder is integrated into an area of 0.41*3.36 mm/sup 2/ achieved by a 0.8- mu m, triple-metal, full-CMOS process. > |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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