Design and Optimization of a Hot-Carrier Resistant High-Voltage nMOS Transistor
| Autor: | M. Annese, S. Carniello, Stefano Manzini |
|---|---|
| Rok vydání: | 2005 |
| Předmět: |
Engineering
business.industry Circuit design Transistor Electrical engineering Integrated circuit layout Electronic Optical and Magnetic Materials law.invention Reliability (semiconductor) law Hardware_INTEGRATEDCIRCUITS Electronic engineering Field-effect transistor Electrical and Electronic Engineering Power MOSFET business NMOS logic Hot-carrier injection |
| Zdroj: | IEEE Transactions on Electron Devices. 52:1634-1639 |
| ISSN: | 0018-9383 |
| DOI: | 10.1109/ted.2005.850625 |
| Popis: | The hot-carrier degradation behavior of a class of high-voltage n-channel drift MOS transistors is experimentally investigated as a function of the geometrical (layout) parameters of the devices. The design restrictions, imposed by reliability requirements, are described as a subset of the space of the geometrical parameters (safe volume) which guarantees a safe hot-carrier operation. The optimization of the specific drain/source on-state resistance of the devices within the safe volume is discussed. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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