The Power PC 601 microprocessor
| Autor: | M.S. Allen, D.P. Tuttle, J.S. Muhich, C.R. Moore, M.C. Becker |
|---|---|
| Rok vydání: | 1993 |
| Předmět: |
Cycles per instruction
Computer science business.industry PowerPC ComputerSystemsOrganization_PROCESSORARCHITECTURES computer.software_genre law.invention IBM POWER microprocessors Microprocessor Power Architecture Hardware and Architecture law Embedded system Superscalar Operating system Cache Electrical and Electronic Engineering business computer Software Back-side bus |
| Zdroj: | IEEE Micro. 13:54-68 |
| ISSN: | 0272-1732 |
| DOI: | 10.1109/40.238002 |
| Popis: | The PowerPC 601 microprocessor, the first of a family of processors based on the PowerPC architecture, is described. The general-purpose processor contains a 32-Kb cache and a superscalar machine organization that allows dispatch and execution of up to three instructions each clock cycle. The bus interface and storage control mechanisms can be configured for a wide range of system designs, from low-cost desktop personal computers to high-performance multi-processor systems. The PowerPC architecture, machine organization, chip packaging technology, and performance are discussed. > |
| Databáze: | OpenAIRE |
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