| Autor: |
Bharat L. Bhuva, Gregory Djaja, Balaji Narasimham, N. J. Gaspard, T. R. Assis, N. N. Mahatme, Karthik Chandrasekharan, J. K. Wang |
| Rok vydání: |
2014 |
| Předmět: |
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| Zdroj: |
2014 IEEE International Reliability Physics Symposium. |
| DOI: |
10.1109/irps.2014.6861095 |
| Popis: |
A novel pulsed-latch design using hysteresis that operates similarly to an edge-triggered flip-flop with improved SER performance is presented. Design was implemented along with standard D-flip-flop (D-FF) and DICE flip-flop in a 20 nm CMOS process. Alpha and Neutron SER test results indicate ~26× and ~3× better SER hardness respectively for the pulsed-hysteresis-latch compared to D-FF. The design also benefits from a 25% higher speed and has a low area overhead of ~8% over the D-FF. A typical processor utilizing the pulsed-hysteresis-latch design can benefit from a ~5× overall SER reduction which is shown to be better than targeted DICE-FF based hardening, both in terms of SER reduction and performance penalty. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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