An algorithm for clock cycle selection in behavioral synthesis
| Autor: | Eugenio Villar, Pedro Tabuenca, Pablo Sánchez |
|---|---|
| Rok vydání: | 1998 |
| Předmět: |
Cycles per instruction
Least slack time scheduling business.industry Computer science Digital clock manager Timing failure Hardware and Architecture High-level synthesis Logic gate Embedded system business Hardware_REGISTER-TRANSFER-LEVELIMPLEMENTATION Software Selection (genetic algorithm) Hardware_LOGICDESIGN CPU multiplier |
| Zdroj: | Journal of Systems Architecture. 44:773-786 |
| ISSN: | 1383-7621 |
| DOI: | 10.1016/s1383-7621(97)00020-9 |
| Popis: | Most of the High Level Synthesis (HLS) tools proposed to date, carry out the synthesis process in clock cycles. This strategy may lead to implementations with a low clock cycle utilization. This problem becomes more important when multicycling is considered. In order to overcome it, we propose determining the clock cycle period during HLS. The technique is based on the minimization of the slack time of the operations thus allowing better clock period selection. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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