A low power 120-to-520Mb/s clock and data recovery circuit for PWM signaling scheme

Autor:	Eun-Ho Yang, Kyongsu Lee, Jin-Ku Kang
Rok vydání:	2015
Předmět:	Phase-locked loop CMOS Sampling (signal processing) Computer science Logic gate Hardware_INTEGRATEDCIRCUITS Electronic engineering Retiming Pulse-width modulation Jitter
Zdroj:	2015 IEEE International Symposium on Circuits and Systems (ISCAS).
Popis:	This paper presents a 120-to-520Mb/s clock and data recovery (CDR) circuit that utilizes pulse width modulation (PWM) signaling scheme. Compared to the conventional approach, the proposed retiming scheme improves sampling margin over 200%, which results in lower BER. The proposed idea has been simulated in a 65nm CMOS technology. The post layout simulation result has shown that recovered clock and data have 3.42ps and 7.55ps rms jitter at 500Mb/s data rate. The CDR circuit consumes 1.97mW (1.2V supply) at 500Mb/s of MIPI M-PHY signaling format.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::23c0af9c8043bf869f25d0b30a8cac8f https://doi.org/10.1109/iscas.2015.7168641 Zobrazit plný text záznamu