Harvard architecture based post processed True random number generator
| Autor: | M. Saranya, A. Kaleel Rahuman, M. Revathy |
|---|---|
| Rok vydání: | 2021 |
| Předmět: |
010302 applied physics
Random number generation Computer science 02 engineering and technology Ring oscillator 021001 nanoscience & nanotechnology 01 natural sciences Power (physics) 0103 physical sciences Verilog 0210 nano-technology Harvard architecture Field-programmable gate array Algorithm computer Randomness Jitter computer.programming_language |
| Zdroj: | Materials Today: Proceedings. 47:135-138 |
| ISSN: | 2214-7853 |
| DOI: | 10.1016/j.matpr.2021.04.019 |
| Popis: | The True random number generation (TRNG) is a process which takes different physical quantities that should be non-deterministic in nature and then they are post processed to reduce potential biases in the random number generation process. The true random number generators are used in various applications like security, cryptography, computer simulation and gaming applications. This work proposed a unique and powerful approach to get random numbers on FPGA by using an unsystematic jitter of ring oscillators. In order to get wide range of variations in the oscillations and to inject jitter into the generated ring oscillator clocks, the free running oscillator rings integrate programmable delay lines (PDL). The primary advantage of the proposed true random number generator is that it regulates the resemblance between many ring oscillators and so it improves the randomness qualities by using PDL. Furthermore, a Harvard architecture based post processing unit is used to eradicate similarities in the generated random numbers. Validation of the suggested solution synthesized on Xilinx with the support of Verilog HDL, and the parameters in terms of area, delay and power are also analyzed. |
| Databáze: | OpenAIRE |
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