Designing new ternary reversible subtractor circuits
Autor: | Asma Taheri Monfared, Majid Haghparast |
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Rok vydání: | 2017 |
Předmět: |
Computer Networks and Communications
Computer science 020208 electrical & electronic engineering 02 engineering and technology 01 natural sciences Reduction (complexity) Logic synthesis Artificial Intelligence Hardware and Architecture 0103 physical sciences Subtractor 0202 electrical engineering electronic engineering information engineering Hardware_ARITHMETICANDLOGICSTRUCTURES Arithmetic 010306 general physics Ternary operation Algorithm Quantum Software Hardware_LOGICDESIGN Electronic circuit Quantum computer |
Zdroj: | Microprocessors and Microsystems. 53:51-56 |
ISSN: | 0141-9331 |
Popis: | The reducing of the width of quantum reversible circuits makes multiple-valued reversible logic a very promising research area. Ternary logic is one of the most popular types of multiple-valued reversible logic, along with the Subtractor, which is among the major components of the ALU of a classical computer and complex hardware. In this paper the authors will be presenting an improved design of a ternary reversible half subtractor circuit. The authors shall compare the improved design with the existing designs and shall highlight the improvements made after which the authors will propose a new ternary reversible full subtractor circuit. Ternary Shift gates and ternary Muthukrishnan–Stroud gates were used to build such newly designed complex circuits and it is believed that the proposed designs can be used in ternary quantum computers. The minimization of the number of constant inputs and garbage outputs, hardware complexity, quantum cost and delay time is an important issue in reversible logic design. In this study a significant improvement as compared to the existing designs has been achieved in as such that with the reduction in the number of ternary shift and Muthukrishnan-Stroud gates used the authors have produced ternary subtractor circuits. |
Databáze: | OpenAIRE |
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