A Hysteresis-Based D-Flip-Flop Design in 28 nm CMOS for Improved SER Hardness at Low Performance Overhead

Autor:	N. J. Gaspard, Karthik Chandrasekharan, Z. Liu, Jeffrey S. Kauppila, Gregory Djaja, Bharat L. Bhuva, Balaji Narasimham, J. K. Wang
Rok vydání:	2012
Předmět:	Nuclear and High Energy Physics Materials science Chip law.invention Hysteresis Logic synthesis Soft error Nuclear Energy and Engineering CMOS Single event upset law Electronic engineering Overhead (computing) Electrical and Electronic Engineering Flip-flop
Zdroj:	IEEE Transactions on Nuclear Science. 59:2847-2851
ISSN:	1558-1578 0018-9499
DOI:	10.1109/tns.2012.2223762
Popis:	A novel D-Flip-Flop design using hysteresis to improve single-event hardness with low performance overhead is presented. Layout-aware sensitive area simulations were used to estimate the improvement in cross-section for the proposed hysteresis DFF (HDFF) vs. a standard DFF. A test chip with the standard DFF, HDFF, and the DICE FF was designed in a 28 nm CMOS process and exposed to alpha, neutron, and heavy-ion beams. The HDFF design shows 14× and 3× improvements in the alpha and neutron SER, respectively, compared with a standard DFF.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::23325af538107a6b28da190dfb2fd4a5 https://doi.org/10.1109/tns.2012.2223762 Zobrazit plný text záznamu