Design of low power 8-bit carry select adder using adiabatic logic
| Autor: | B. S. Premananda, M. K. Chandana, K. P. Shree Lakshmi, A. M. Keerthi |
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| Rok vydání: | 2017 |
| Předmět: |
Adder
Signal processing Computer science 0211 other engineering and technologies 8-bit 02 engineering and technology 020202 computer hardware & architecture Power (physics) CMOS Logic gate 021105 building & construction 0202 electrical engineering electronic engineering information engineering Electronic engineering Carry-select adder Hardware_LOGICDESIGN Electronic circuit |
| Zdroj: | 2017 International Conference on Communication and Signal Processing (ICCSP). |
| DOI: | 10.1109/iccsp.2017.8286696 |
| Popis: | Computational speed of basic data path elements such as adders plays a crucial role in performance of digital and signal processing systems. Among various adder architectures, carry select adder (CSLA) has better performance in terms of speed in comparison with others. However, this merit is accompanied by its high power dissipation and area occupancy due to redundant computing elements used in each stage hence limiting its application. Power dissipation in these adders can be minimized by various low power implementation techniques such as reversible logic gates, multi-V th approach, and adiabatic logic. Among these low power approaches, adiabatic logic proves to be more efficient in comparison with other low power approaches. In the proposed work, 180 nm CMOS technology in CADENCE environment is used to carry out the design and analysis of both conventional and proposed CSLA architectures. Power dissipation in this proposed 8-bit CSLA architecture reduces by about 82% as compared to conventional 8-bit CSLA adder architecture. Further, the computational delay is also reduced when compared with the conventional 8-bit CSLA architecture. It is noteworthy that delay in adiabatic logic circuits greatly depends on frequency of operation [1]. |
| Databáze: | OpenAIRE |
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