A 51.2GOPS 1.0GB/s-DMA single-chip multi-processor integrating quadruple 8-way VLIW processors

Autor:	Hiroshi Okano, Yukihito Kawabe, Atsuhiro Suga, A. Sato, Tetsutaro Hashimoto, Shinichiro Tago, Hideo Miyake, Kenichi Kawasaki, T. Shiota, Yasuki Nakamura, W. Shibamoto, Hiromasa Takahashi, Fumihiko Hayakawa
Rok vydání:	2005
Předmět:	Single chip Computer science business.industry Multiprocessing ComputerSystemsOrganization_PROCESSORARCHITECTURES Multi processor Chip Very long instruction word Embedded system Hardware_INTEGRATEDCIRCUITS business Cmos process Direct memory access Decoding methods
Zdroj:	ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..
Popis:	A 51.2-GOPS chip multi-processor integrates four 8-way VLIW embedded processors with 1.0 GB/s local-bus direct memory access. This IC completes MPEG2 MP@HL video-stream decoding at 68% of its processor capability without dedicated hardware. The 11.9 mm /spl times/ 10.3 mm chip is fabricated in a 90 nm 9M CMOS process and consumes 5 W at 533 MHz.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::22bba9fc0c1a0bf2574dcba604ece6cb https://doi.org/10.1109/isscc.2005.1493935 Zobrazit plný text záznamu