An automatic temperature compensation of internal sense ground for subquarter micron DRAM's
| Autor: | Kiyohiro Furutani, Hideyuki Ozaki, Yuichiro Komiya, Mikio Asakura, Tsukasa Ooishi, Hideto Hidaka, Kenichi Yasuda, Kei Hamade, Hiroshi Miyamoto |
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| Rok vydání: | 1995 |
| Předmět: |
Engineering
business.industry Subthreshold conduction Transistor Electrical engineering Hardware_PERFORMANCEANDRELIABILITY Sense (electronics) law.invention Threshold voltage Reliability (semiconductor) law Hardware_INTEGRATEDCIRCUITS Electrical and Electronic Engineering business Low voltage Dram Voltage |
| Zdroj: | IEEE Journal of Solid-State Circuits. 30:471-479 |
| ISSN: | 0018-9200 |
| DOI: | 10.1109/4.375968 |
| Popis: | This paper describes DRAM array driving techniques and the parameter scaling techniques for low voltage operation using the boosted sense ground (BSG) scheme and further improved methods. Temperature compensation and adjustable internal voltage levels maintain a small subthreshold leakage current for a memory cell transistor (MC-Tr), and a distributed BSG (DBSG) scheme and a column decoded sensing (CDS) scheme achieve the effective scaling. These schemes can set the DRAM array free from the leakage current problem and the influence of temperature variations. Therefore, parameters for the MC-Tr, threshold voltage (V/sub th/), and the boosted voltage for the gate bias can be scaled down, and it is possible to determine the V/sub th/ of the MC-Tr simply (0.45 V at K=0.4) for the satisfaction of the small leakage current, for high speed and stable operation, and for high reliability (V/sub PP/ is below 2 V/sub CC/). They are applicable to subquarter micron DRAM's of 256 Mb and more. > |
| Databáze: | OpenAIRE |
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