| Autor: |
K. Satoh, T. Hotta, N. Kanekawa, R. Fujita, Y. Takahashi, T. Hirotsu, H. Yamada, K. Tomobe, S. Yamaguchi, Kotaro Shimamura, N. Miyazaki |
| Rok vydání: |
2003 |
| Předmět: |
|
| Zdroj: |
AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360). |
| DOI: |
10.1109/apasic.1999.824026 |
| Popis: |
A chip level redundant self-checking fail-safe microprocessor has been developed using a 0.35 /spl mu/m CMOS embedded gate array. The microprocessor integrates two synthesizable processor cores and a self-checking comparator in a single chip. A full-custom processor core was transformed into each of the synthesizable cores for this purpose. Design methodologies suitable for reusing synthesizable processor cores has also been developed. Developed synthesizable processor cores and design methodologies reduce the cost of process migration of the chip. Migrating to the newer process improves the performance of the developed microprocessor with low development cost. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
|
