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This paper presents the use of one hot residue (OHR) number system (NS) for digital signal processing and designing of arithmetic circuits for high speed and low power applications. The best highlight of this scheme is that the delay of implementation is equal to delay of a transistor which has proved to be a good improvement in comparison to conventional methods. The other advantages of using residue (OHR) could be simplicity of implementation and minimum power dissipation. The work presented here would mainly focus on design of adder, subtractor, multiplier, and other arithmetic units, which are commonly used in the design of filters with selected moduli set based on one hot coding technique. These subsystems are utilized to design the FFT computation block using one hot encoding technique. The constituent units involved in the FFT computation block design based on OHRNS and Conventional approaches, are implemented using standard CMOS 250 nm technology using Tanner EDA tool thus providing comparative analysis. The experimental results shows that FFT computation block based on one hot encoding are faster and consume less number of implementation transistors than similar hardware implementations (conventional techniques) making it a viable option for efficient designs. |
