Efficient Post-layout Power-Delay Curve Generation

Autor:	Carl Sechen, Miodrag Vujkovic, David Wadkins
Rok vydání:	2005
Předmět:	Adder Logic block Computer science Design flow Real-time computing Power (physics) VHDL Hardware_INTEGRATEDCIRCUITS Verilog Power semiconductor device Parasitic extraction computer Simulation Hardware_LOGICDESIGN computer.programming_language Block (data storage)
Zdroj:	Lecture Notes in Computer Science ISBN: 9783540290131 PATMOS
Popis:	We have developed a complete design flow from Verilog/VHDL to layout that generates what is effectively a post-layout power versus delay curve for a digital IC block. Post-layout timing convergence is rapid over the entire delay range spanned by a power versus delay tradeoff curve. The points on the gate-sizing generated power-delay curve, when actually laid out, are extremely close in transistor-level simulated power and delay, using full 3D extracted parasitics. The user can therefore confidently obtain any feasible post-layout power-delay tradeoff from the power-delay curve for a logic block. To the best of our knowledge, this is the first report of such a post-layout capability.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::21dcef3b2b8f0f6a5f8c3880b62bfa2c https://doi.org/10.1007/11556930_41 Zobrazit plný text záznamu