A class of almost-optimal size-independent parallel prefix circuits
| Autor: | Hatem M. El-Boghdadi |
|---|---|
| Rok vydání: | 2013 |
| Předmět: |
Adder
Computer Networks and Communications Parallel algorithm Class (philosophy) Hardware_PERFORMANCEANDRELIABILITY Time step Upper and lower bounds Theoretical Computer Science Artificial Intelligence Hardware and Architecture Parallel prefix Hardware_INTEGRATEDCIRCUITS Equivalent circuit Algorithm Software Hardware_LOGICDESIGN Electronic circuit Mathematics |
| Zdroj: | Journal of Parallel and Distributed Computing. 73:888-894 |
| ISSN: | 0743-7315 |
| DOI: | 10.1016/j.jpdc.2013.03.012 |
| Popis: | Prefix computation is one of the fundamental problems that can be used in many applications such as fast adders. Most proposed parallel prefix circuits assume that the circuit is of the same width as the input size. In this paper, we present a class of parallel prefix circuits that perform well when the input size, n, is more than the width of the circuit, m. That is, the proposed circuit is almost optimal in speed when n>m. Specifically, we derive a lower bound for the depth of the circuit, and prove that the circuit requires one time step more than the optimal number of time steps needed to generate its first output. We also show that the size of the circuit is optimal within one. The input is divided into subsets, each of width m-1, and presented to the circuit in subsequent time steps. The circuit is compared with functionally similar circuits of (Lin, 1999 [9]; Lin and Hung, 2009 [12]) to show its outperforming speed. When n>m, the circuit is shown to be faster than the family of waist-size optimal circuits with waist 1 (WSO-1) of the same width and fan-out. |
| Databáze: | OpenAIRE |
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