45nm low-power CMOS SoC technology with aggressive reduction of random variation for SRAM and analog transistors

Autor:	F. Hou, Obradovic Borna J, Samuel Martin, T. Blythe, H. Yang, S. Liu, Shashank S. Ekbote, Greg C. Baldwin, Kamel Benaissa, Theodore W. Houston, A. Singh, Hisashi Shichijo, Richard J. K. Taylor
Rok vydání:	2008
Předmět:	Bit cell Engineering business.industry Transistor Electrical engineering law.invention CMOS law visual_art Low-power electronics Electronic component visual_art.visual_art_medium Electronic engineering System on a chip Static random-access memory business Electronic circuit
Zdroj:	2008 Symposium on VLSI Technology.
Popis:	Mobile system-on-chip (SoC) technologies require high-quality analog active and passive components along with low-power CMOS and dense SRAM. However, area scaling for both the SRAM bit cell and analog CMOS circuits is becoming increasingly difficult due to the impact of transistor random variation. To avoid added cost, co-optimizing the process for low random variation along with high performance and low power is required. We report a 45 nm lowpower technology with significantly reduced random variation for high yielding 0.255 mum2 SRAM arrays and analog transistors. Flexible RF and passive components for mobile SoCpsilas are also described. These process techniques enable continued 50% area scaling at 45 nm and beyond.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::2168e0c61b61147780eef63d8b5bebf0 https://doi.org/10.1109/vlsit.2008.4588602 Zobrazit plný text záznamu