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The paper describes an enhanced logical effort model (LEM) to consider UDSM effects in delay calculations. As complex and large fan-in cells can result in an optimized realization of designs, the enhanced LEM is used to determine the stack length criteria as a limit of the cell complexity allowed for technology partitioning in a library-free logic synthesis paradigm. The enhanced LEM has shown to be within 5% accuracy for simple gates and 10% accuracy for complex gates. The stack lengths for four separate technology nodes (90nm, 65nm, 45nm and 32nm) are determined for both AOI and OAI implementations. |
