Improved binary‐weighted split‐capacitive‐array DAC for high‐resolution SAR ADCs
Autor: | Yuan Xing Li, Yong Lian |
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Rok vydání: | 2014 |
Předmět: |
Engineering
business.industry Capacitive sensing Digital-to-analog converter Binary number Linearity Hardware_PERFORMANCEANDRELIABILITY Capacitance law.invention Capacitor Least significant bit Most significant bit law Hardware_INTEGRATEDCIRCUITS Electronic engineering Electrical and Electronic Engineering business Computer hardware Hardware_LOGICDESIGN |
Zdroj: | Electronics Letters. 50:1194-1195 |
ISSN: | 1350-911X 0013-5194 |
DOI: | 10.1049/el.2014.1752 |
Popis: | An improved split-capacitive-array digital-to-analogue converter (DAC) with an optimised segmentation degree (i.e. the number of bits in the most significant bit (MSB) sub-array) is proposed to reduce the area, the switching power consumption and improve the linearity compared to a conventional binary-weighted (CBW) capacitive-array DAC and a conventional binary-weighted split-capacitive-array with an attenuation capacitor (BWA) DAC. The presented analysis considers the area and the power dissipation from the DAC as well as the analogue-to-digital converter's (ADC's) dynamic performance to determine the optimum segmentation degree for the proposed split-capacitive-array DAC and the BWA DAC. Using the minimum matching requirement for the unit capacitor in a 12-bit CBW DAC, the proposed split-capacitive-array DAC with an MSB:LSB = 8:4 segmentation reduces the input capacitance by 2× and reduces the switching power by 15× compared to the 12-bit CBW DAC. It also improves the ADC's dynamic performance and reduces the switching power by 3.75× compared to the conventional 12-bit BWA DAC with an MSB:LSB = 10:2 segmentation. |
Databáze: | OpenAIRE |
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