A 60 ns 256Kx1 bit DRAM using LD/SUP 3/ technology and double-level metal interconnection
| Autor: | R.A. Kertis, K.B. Ohri, K.J. Fitzpatrick |
|---|---|
| Rok vydání: | 1984 |
| Předmět: |
Interconnection
Engineering Hardware_MEMORYSTRUCTURES business.industry Circuit design Electrical engineering Semiconductor memory Mixed-signal integrated circuit Capacitance Matrix (mathematics) Hardware_INTEGRATEDCIRCUITS Electronic engineering Electrical and Electronic Engineering business Dram Access time |
| Zdroj: | IEEE Journal of Solid-State Circuits. 19:585-590 |
| ISSN: | 1558-173X 0018-9200 |
| DOI: | 10.1109/jssc.1984.1052193 |
| Popis: | A high-speed 256K/spl times/1-bit DRAM, using new circuit design techniques and a scaled n-channel process, has been developed. A row access time of 60 ns has been achieved through the use of short-channel devices and two levels of low-resistance interconnect. A staggered matrix precharge was implemented to reduce peak supply current and dI/dt during row precharge. Supply current transients are particularly important at the 256K density level due to the fast cycle rates (approaching 10 MHz) and the large matrix capacitance to be precharged. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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