| Autor: |
Hanh-Phuc Le, Po-Hung Chen, Rimas Avizienis, Pi-Feng Chiu, Stevo Bailey, Krste Asanovic, Brian Richards, Ben Keller, Ruzica Jevtic, Brian Zimmer, Borivoje Nikolic, Nicholas Sutardja, Elad Alon, Yunsup Lee, Milovan Blagojevic, Jaehwa Kwak, Andrew Waterman, Alberto Puggelli, Philippe Flatresse |
| Rok vydání: |
2015 |
| Předmět: |
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| Zdroj: |
VLSIC |
| DOI: |
10.1109/vlsic.2015.7231305 |
| Popis: |
This work demonstrates a RISC-V vector microprocessor implemented in 28nm FDSOI with fully-integrated non-interleaved switched-capacitor DCDC (SC-DCDC) converters and adaptive clocking that generates four on-chip voltages between 0.5V and 1V using only 1.0V core and 1.8V IO voltage inputs. The design pushes the capabilities of dynamic voltage scaling by enabling fast transitions (20ns), simple packaging (no off-chip passives), low area overhead (16%), high conversion efficiency (80–86%), and high energy efficiency (26.2 DP GFLOPS/W) for mobile devices. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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