Area-Time Efficient Hardware Architecture for Signature Based on Ed448
| Autor: | Mojtaba Bisheh-Niasar, Reza Azarderakhsh, Mehran Mozaffari Kermani |
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| Rok vydání: | 2021 |
| Předmět: |
Hardware architecture
Computer science business.industry Karatsuba algorithm Digital Signature Algorithm Digital signature Embedded system Distributed memory Hardware_ARITHMETICANDLOGICSTRUCTURES Electrical and Electronic Engineering Elliptic curve cryptography business Field-programmable gate array Throughput (business) |
| Zdroj: | IEEE Transactions on Circuits and Systems II: Express Briefs. 68:2942-2946 |
| ISSN: | 1558-3791 1549-7747 |
| DOI: | 10.1109/tcsii.2021.3068136 |
| Popis: | In this brief, we proposed a highly-optimized FPGA-based implementation of the Ed448 digital signature algorithm. Despite significant progress in elliptic curve cryptography (ECC) implementations, Ed448 hardware architecture, to the best of our knowledge, has not been investigated in the literature. In this work, we demonstrate a high throughput while maintaining low resource architecture for Ed448 by employing a new combined algorithm for refined Karatsuba-based multiplier with precise scheduling. Furthermore, a compact distributed memory unit is developed to increase speed while keeping the area low. Our variable-base-point Ed448 architecture performs 327 signatures and 189 verifications per second at a notably higher security level of 224 bits, using not more than 6,617 Slices and 16 DSPs on a Xilinx Artix-7 FPGA. We also proposed possible countermeasures and extensions to Ed448 to counter the physical attacks. |
| Databáze: | OpenAIRE |
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