| Autor: |
Hiroshi Okano, T. Satoh, Hiroshi Takahashi, M. Saito, H. Utsumi, T. Katayama, T. Saruwatari, Y. Takebe, M. Kimura, M. Tsuji, Hideo Miyake, Atsuhiro Suga, T. Sukemura, Yoshio Hirose |
| Rok vydání: |
2002 |
| Předmět: |
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| Zdroj: |
Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434). |
| DOI: |
10.1109/apasic.2000.896984 |
| Popis: |
A 4-way VLIW microprocessor based on an improved VLIW architecture is developed for embedded application in a 0.18 /spl mu/m 5-layer-metal CMOS process. This processor equips a 2-way integer pipeline and a 2-way floating/media pipeline. Each floating pipeline and media pipeline has 2-parallel and 4-parallel SIMD mechanisms, respectively. The processor equips separate instruction and data caches; each of 16 KB size and 4-way set associative. 6.7 M transistors are integrated in an area of 7.5 mm/spl times/7.5 mm. We also developed companion chip which is used together with the processor. Companion chip is fabricated using a 0.25 /spl mu/m 4-layer-metal CMOS process. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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