| Autor: |
L. Hudepohl, R. Allmon, S. Samudrala, D.E. Dever, J. Farrell, R.C. Marcello, D.E. Sanders, J. Lundberg, N. Fitzgerald, M. Richesson, J. Grodstein, L. Chao, B.J. Benschneider, J.D. Pickholtz, M. Callander, Soha Hassoun, D. Kravitz, S. Marino, R.P. Preston |
| Rok vydání: |
1990 |
| Předmět: |
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| Zdroj: |
1990 37th IEEE International Conference on Solid-State Circuits. |
| DOI: |
10.1109/isscc.1990.110123 |
| Popis: |
The system, process, and design implications of converting a microprocessor chip set originally implemented in a 5-V, 1.5- mu m (drawn) CMOS process to one implemented in a 3.3-V, 1.0- mu m (drawn) CMOS process are described. The chip set is 75% faster than the previous generation and comprises a processor chip, a floating-point chip, a cache controller chip, and a clock chip. It operates at 62.5 MHz under worst-case conditions. Micrographs of each design are given. Power and packaging specifications for each chip and the 3.3-V, 1.0- mu m (drawn) process specifications are tabulated. A high-temperature schmoo plot for the CPU chip is also given. > |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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