| Popis: |
We present an overview of partially-depleted silicon-on-insulator (PD-SOI) CMOS transistor technologies for high-performance microprocessors. To achieve a “high performance per watt” figure of merit, transistor technology elements like PD-SOI, strained Si, aggressive junction scaling, and asymmetric devices need hand-in-hand development with multiple-core and power-efficient designs. These techniques have been developed, applied, and optimized for 45nm SOI volume manufacturing at GLOBALFOUNDRIES in Dresden. To enable further transistor scaling to 32nm design rules, high-K metal-gate (HKMG) technology is key. Gate-first and replacement-gate HKMG integration as well as future strained Si technologies like strained silicon directly bonded on SOI and embedded Si:C are discussed. |
