| Autor: |
Philippe Candelier, R. Ranica, B. Allard, Pierre Malinge, Richard Fournel, Alexandre Villaret, Francois Jacquet, S. Martin, Pascale Mazoyer |
| Rok vydání: |
2005 |
| Předmět: |
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| Zdroj: |
Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005.. |
| DOI: |
10.1109/vlsic.2005.1469404 |
| Popis: |
An 8 Mbit memory chip featuring a floating body one transistor cell on bulk substrate is characterized for the first time. A high-speed and high accuracy current sense-amplifier with a large common mode reference current is proposed. It achieves a reading time of 10 ns and a current read margin lower than 5 /spl mu/A. A bit fail rate of 0.017% was measured on a 1 Mbit module. Data retention shows that 1 Tbulk cell concept has the potential to be used as a future eDRAM memory cell. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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