Design of a DCO based on worst-case delay of a self-timed counter and a digitally controllable delay path

Autor: Oyinkuro Benafa, Austin Ogweno, Alex Yakovlev, Delong Shang
Rok vydání: 2016
Předmět:
Zdroj: NEWCAS
DOI: 10.1109/newcas.2016.7604821
Popis: Delay path reconfiguration is used to control frequency output in Digitally Controlled Oscillators. In order to achieve a very low frequency range, if the delay path is not properly designed, this would result in large area overhead and leakage power loss. An alternative delay path is proposed for the DCO, based on a unit delay as the smallest possible delay, with added architecture to multiply the unit delay using digital control bits, this allows the delay output to be near-linear. The proposed delay path has two control modes, a 2-bits fine grain control and 6-bit coarse control. Simulation results show that the frequency of the DCO ranges from 34.92MHz to 448MHZ at 1.1V with maximum average power consumption of 358.27µW at 1.1V.
Databáze: OpenAIRE