A Statistical Algorithm for Power- and Timing-Limited Parametric Yield Optimization of Large Integrated Circuits
| Autor: | Yaping Zhan, Michael Orshansky, Anirudh Devgan, Murari Mani |
|---|---|
| Rok vydání: | 2007 |
| Předmět: |
Engineering
Mathematical optimization business.industry Robust optimization Integrated circuit Computer Graphics and Computer-Aided Design Sizing law.invention Design for manufacturability law Robustness (computer science) Algorithm design Electrical and Electronic Engineering business Software Parametric statistics Quantile |
| Zdroj: | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 26:1790-1802 |
| ISSN: | 0278-0070 |
| DOI: | 10.1109/tcad.2007.895797 |
| Popis: | Variability in process parameters leads to a significant parametric yield loss of high-performance ICs due to the large spread in leakage-power consumption and speed of chips. In this paper, we propose an algorithm for total power minimization under timing constraints in the presence of variability. The algorithm is formulated as a robust optimization program with a guarantee of power and timing yields, with both power and timing metrics being treated probabilistically. Power reduction is performed by simultaneous sizing and dual threshold-voltage assignment. An extremely fast run-time is achieved by casting the problem as a second-order conic problem and solving it using efficient interior-point optimization methods. The performance of the algorithm was evaluated on a variety of public and industrial benchmarks, with a library characterized using 70-nm Berkeley Predictive Technology Model. When compared to the deterministic optimization, the new algorithm, on average, reduces static power and total power at the 99.9th quantile by 31% and 17%, respectively, without loss of parametric yield. The run-time on the benchmarks is 30times faster than other known statistical power-minimization algorithms. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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