| Autor: |
Neerja Bawaskar, Fadi Batarseh, Davide Pacifico, Atul Chittora, Shenghua Song, Monisa Ramesh Babu, Shobhit Malik, Janam Bakshi |
| Rok vydání: |
2020 |
| Předmět: |
|
| Zdroj: |
International Symposium for Testing and Failure Analysis. |
| ISSN: |
0890-1740 |
| DOI: |
10.31399/asm.cp.istfa2020p0352 |
| Popis: |
Many fabless customers do not share the design information such as LEF/DEF (Library Exchange Format and Design Exchange Format), design netlist, and test program information with foundries because they contain proprietary IP. Determining the root-cause of defects on such products only based on Sort test results and no scan diagnostics [1] for logic chips can be quite challenging. This paper presents a new layout pattern analysis methodology to isolate the failing weak layout structure using only the sort test results and the product GDS layout. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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