Performance Improvement of Delta-Sigma ADC/DAC/TDC Using Digital Technique
| Autor: | Jun-ya Kojima, Jianlong Wang, Jiang-Lin Wei, Yuanyang Du, Nene Kushita, Haruo Kobayashi, Masahiro Murakami |
|---|---|
| Rok vydání: | 2018 |
| Předmět: |
Reduction (complexity)
Computer science Limit cycle 020208 electrical & electronic engineering 0202 electrical engineering electronic engineering information engineering Electronic engineering 02 engineering and technology Dither Performance improvement Delta-sigma modulation 020202 computer hardware & architecture |
| Zdroj: | 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT). |
| DOI: | 10.1109/icsict.2018.8565014 |
| Popis: | This paper reviews the authors’ group research results of data-weighted averaging (DWA) algorithm for multi-bit ΔΣADC/DAC/TDC and also dithering techniques for ΔΣ ADC/DAC for limit cycle reduction. When a multi-bit internal DAC or digital-to-time converter (DTC) is used inside a modulator, nonlinearities of the DAC/DTC are not noise-shaped and the SNR of the ΔΣADC/DAC/TDC degrades. To overcome this problem, we investigate several algorithms to noise-shape the DAC/DTC nonlinearities. Also we investigate limit cycle suppression techniques in ΔΣDAC. Then we discuss their generalization. |
| Databáze: | OpenAIRE |
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