Multiclock selection and synthesis for CDFGs using optimal clock sets and genetic algorithms
| Autor: | J.P. Knight, E. Torbey |
|---|---|
| Rok vydání: | 2001 |
| Předmět: |
Very-large-scale integration
Automatic control Computer science Iterative method Circuit design Real-time computing Matrix clock Digital clock manager Integrated circuit design Timing failure Clock synchronization Hardware and Architecture High-level synthesis Genetic algorithm Electrical and Electronic Engineering Algorithm Software |
| Zdroj: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 9:599-607 |
| ISSN: | 1557-9999 1063-8210 |
| DOI: | 10.1109/92.953494 |
| Popis: | Selecting a clock period is an essential step in implementing hardware from behavioral descriptions. Current methods either estimate the clock prior to scheduling or involve exhaustive runs of the high-level synthesis tools to obtain a globally optimum clock period. Further, the potential benefits of allowing the use of multiple clocks for performance optimization has not been investigated. This paper presents a clock selection method that works simultaneously with synthesis by selecting a clock from an optimal clock set. The synthesis is iterative and is optimized by evolutionary techniques. The method is very flexible and can accommodate a large set of potentially optimal clocks. We also present multirate clock synthesis with path-dependent clock selection where different paths in a control data flow graph (CDFG) are optimized with different clock periods. The results shown prove the method's effectiveness. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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