Architecture of high performance successive approximation time digitizer

Autor: Ryoji Shiota, Takashi Ida, Yuki Ozawa, Haruo Kobayashi, Jiang Richen, Shotaro Sakurai, Hirotaka Arai, Nobukazu Tsukiji, Seiya Takigami
Rok vydání: 2017
Předmět:
Zdroj: ISPACS
DOI: 10.1109/ispacs.2017.8266522
Popis: This paper describes three techniques for a high performance successive-approximation-register time-to-digital converter (SAR TDC) measuring the time difference between two timing signals. (1) Two-step SAR TDC configuration for fine time resolution and small circuit as well as low power. (2) Algorithm for absolute value measurement of time difference: estimation of delay values τ 1 , τ 2 and their disagreement correction using extra buffers of τ 2 . Employment of trigger circuits in front of the SAR TDC for measurement of not only repetitive timing signal but also one shot timing signal. We show their principles, circuit configurations, operations, and simulation results.
Databáze: OpenAIRE