A Power-Aware Toggling-Frequency Actuator in Data-Toggling SRAM for Secure Data Protection
| Autor: | Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Tony Tae-Hyoung Kim |
|---|---|
| Rok vydání: | 2021 |
| Předmět: |
business.industry
Computer science Transistor Electrical engineering 020206 networking & telecommunications Hardware_PERFORMANCEANDRELIABILITY 02 engineering and technology 020202 computer hardware & architecture law.invention Power (physics) Frequency divider CMOS law Duty cycle Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Clock generator Static random-access memory Electrical and Electronic Engineering business Actuator Hardware_LOGICDESIGN |
| Zdroj: | IEEE Transactions on Circuits and Systems II: Express Briefs. 68:2122-2126 |
| ISSN: | 1558-3791 1549-7747 |
| Popis: | We propose a power-aware toggling-frequency actuator for an 1K-byte data-toggling SRAM. The actuator periodically toggles the stored data to balance the voltage stress in the SRAM cells to secure against data imprinting attacks. Our proposed actuator has three key features. First, our proposed actuator embodies a small duty cycle clock divider to divide the main clock and generate two toggling clocks. The small duty cycle clock minimizes toggling transistor turn-on time and reduces the leakage power in stand-by operation. Second, it leverages on the main clock of the data-toggling SRAM to generate the toggling clock without an additional clock generator. Third, our proposed actuator can scale the data toggling operation between high frequency for highly secure applications, and low frequency for low power applications. We implemented the 1K-byte data-toggling SRAM with the proposed toggling-frequency actuator based on 65nm CMOS technology. At higher toggling frequency (~ 1MHz), the data-toggling SRAM features less than 5% imprinting effect. At lower toggling frequency (~ 10kHz), the SRAM dissipates $\times $ power product. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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