Modified Dual-CLCG Method and its VLSI Architecture for Pseudorandom Bit Generation
| Autor: | Amit Kumar Panda, Kailash Chandra Ray |
|---|---|
| Rok vydání: | 2019 |
| Předmět: |
Pseudorandom number generator
Very-large-scale integration business.industry Computer science 020208 electrical & electronic engineering Clock rate Maximum length sequence Cryptography 02 engineering and technology Hardware and Architecture Linear congruential generator 0202 electrical engineering electronic engineering information engineering NIST Electrical and Electronic Engineering business Field-programmable gate array Computer hardware |
| Zdroj: | IEEE Transactions on Circuits and Systems I: Regular Papers. 66:989-1002 |
| ISSN: | 1558-0806 1549-8328 |
| DOI: | 10.1109/tcsi.2018.2876787 |
| Popis: | Pseudorandom bit generator (PRBG) is an essential component for securing data during transmission and storage in various cryptography applications. Among popular existing PRBG methods such as linear feedback shift register (LFSR), linear congruential generator (LCG), coupled LCG (CLCG), and dual-coupled LCG (dual-CLCG), the latter proves to be more secure. This method relies on the inequality comparisons that lead to generating pseudorandom bit at a non-uniform time interval. Hence, a new architecture of the existing dual-CLCG method is developed that generates pseudo-random bit at uniform clock rate. However, this architecture experiences several drawbacks such as excessive memory usage and high-initial clock latency, and fails to achieve the maximum length sequence. Therefore, a new PRBG method called as “modified dual-CLCG” and its very large-scale integration (VLSI) architecture are proposed in this paper to mitigate the aforesaid problems. The novel contribution of the proposed PRBG method is to generate pseudorandom bit at uniform clock rate with one initial clock delay and minimum hardware complexity. Moreover, the proposed PRBG method passes all the 15 benchmark tests of NIST standard and achieves the maximal period of $2^{n}$ . The proposed architecture is implemented using Verilog-HDL and prototyped on the commercially available FPGA device. |
| Databáze: | OpenAIRE |
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