3.4 A 10nm FinFET 2.8GHz tri-gear deca-core CPU complex with optimized power-delivery network for mobile SoC performance
| Autor: | Ray Tzeng, Cheng-Yuh Wu, Taner Dosluoglu, Chi-Hsueh Wang, Jin Son, David Yen, Hugh Mair, Girishankar Gurumurthy, Yi-Chang Zhuang, Wuan Kuo, Yuwen Tsai, Hung-Wei Wang, Ue Fu, Rolf Lagerquist, Kent Li, Achuta Thippana, Sumanth Gururajarao, Tony Hsieh, Ping Kao, Alice Wang, Mark Shane Peng, Gordon Lin, Jengding Wu, Anatoly Gelman, Daniel Dia, Lin Wen-Yi, Uming Ko, Gordon Gammie, Manzur Rahman, Ericbill Wang |
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| Rok vydání: | 2017 |
| Předmět: |
010302 applied physics
Computer science business.industry Circuit design 020208 electrical & electronic engineering Transistor 02 engineering and technology 01 natural sciences Computational science law.invention Power (physics) law Embedded system 0103 physical sciences 0202 electrical engineering electronic engineering information engineering CPU core voltage Central processing unit business |
| Zdroj: | ISSCC |
| Popis: | This paper describes logic and circuit design features of a heterogeneous tri-cluster deca-core CPU complex incorporated into a 10nm FinFET mobile SoC for smartphone applications. Similar to Helio X20 [1], the Deca-Core compute function contains three separate clusters of ARMv8a CPUs. The high-performance (HP) cluster is updated to incorporate the most power-efficient out-of-order Cortex-A73 CPU, operating at max frequency of 2.8GHz. In X20, the low-power (LP) and ultra-low power (ULP) clusters used Cortex-CA53 with different implementation flows, while this work achieves a +44% more power-efficient ULP solution based on the newer Cortex-CA35 CPU (Fig. 3.4.1). In addition, the LP cluster achieves a +36% more performance than ULP or +40% more power-efficiency than the HP cluster, for optimal sustainable performance/power applications including augmented reality and virtual reality (AR/VR). A die photograph, Fig. 3.4.7, highlights the three CPU clusters. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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