High voltage MOSFETs integration on advanced CMOS technology: Characterization of thick gate oxides incorporating high k metal gate stack from logic core process
| Autor: | Alain Toffoli, Loic Welter, J. P. Reynard, C. Jahan, Franck Julien, E. Richard, Dann Morillon, Pascal Masson, Jean Coignus |
|---|---|
| Rok vydání: | 2017 |
| Předmět: |
010302 applied physics
Materials science business.industry Gate dielectric Electrical engineering Time-dependent gate oxide breakdown Hardware_PERFORMANCEANDRELIABILITY 02 engineering and technology 021001 nanoscience & nanotechnology 01 natural sciences CMOS Hardware_GENERAL Gate oxide Logic gate 0103 physical sciences Hardware_INTEGRATEDCIRCUITS Optoelectronics 0210 nano-technology business Metal gate Gate equivalent Hardware_LOGICDESIGN High-κ dielectric |
| Zdroj: | 2017 International Conference of Microelectronic Test Structures (ICMTS). |
| DOI: | 10.1109/icmts.2017.7954274 |
| Popis: | This paper presents the performance and reliability evaluation of high voltage MOS gate stacks integrated in an advanced CMOS technology platform. The aim of this study is to evaluate the compatibility of a thick silicon dioxide with a high-k metal gate stack which replaces the standard polysilicon gate. Using capacitors, physical, electrical, and reliability characterizations are carried out and TiN metal gate is found to be a potential issue as it induces a high density of interfacial traps. Despite these traps, oxide lifetime could still meet demanding requirements. Thus, using the high-k metal gate stack on top of a thick SiO 2 gate oxide could be a potential solution for high voltage transistors integration on advanced CMOS platforms with embedded non-volatile memories. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|