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In current processors, the cache controller, which contains the cache directory and other logic such as tag comparators, is active for each instruction fetch and is responsible for 20-25% of the power consumed in the Icache. Reducing the power consumed by the cache controller is important for low power I-cache design. We present three architectural modi cations, which in concert, allow us to reduce the cache controller activity to less than 2% for most applications. The rst modi cation involves comparing cache tags for only those instructions that result in fetches from a new cache block. The second modi cation involves the tagging of those branches that cause instructions to be fetched from a new cache block. The third modi cation involves augmenting the I-cache with a small on-chip memory called the S-cache. The most frequently executed basic blocks of code are statically allocated to the S-cache before program execution. We present empirical data to show the e ect that these modi cations have on the cache con |
