An Optimized Flow for Designing High-Speed, Large-Scale CMOS ASIC SoCs

Autor:	Werner Haas, Ulrich Heinkel, S. Gossens, Claus Mayer, Charles F. Webb, Hans Sahm
Rok vydání:	2004
Předmět:	Computer science business.industry Synchronous optical networking Hardware description language Design flow Formal methods Application-specific integrated circuit Embedded system VHDL Hardware_INTEGRATEDCIRCUITS Netlist System on a chip business computer computer.programming_language
Zdroj:	Lecture Notes in Computer Science ISBN: 9783540223771 SAMOS
Popis:	This paper describes our state-of-the-art design flow used for specification, implementation and verification of a 10 million gates ASIC System-on-Chip (SoC) for a Sonet/SDH application. We present our tools and methodologies currently used and/or being developed for a multisite ASIC design project from the first specification up to the gate level netlist: our multi-site data management environment VHDLDevSys, our multi-use and re-use library ADK-Lib and our multi-platform VHDL/C++ simulation/verification environment PROVerify together with the employment of formal methods.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::1d5b2bb6bb200b0d62831c2159057efc https://doi.org/10.1007/978-3-540-27776-7_11 Zobrazit plný text záznamu