Impact and damage on deep sub-micron CMOS technology induced by substrate current due to ESD stress
| Autor: | Michel Vallet, J. Beltritti, Philippe Galy, E. Petit, Sylvain Dudit, Christophe Entringer, C. Richier, Frank Jezequel |
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| Rok vydání: | 2009 |
| Předmět: |
Electrostatic discharge
Materials science Silicon business.industry chemistry.chemical_element Substrate (electronics) Condensed Matter Physics Atomic and Molecular Physics and Optics Surfaces Coatings and Films Electronic Optical and Magnetic Materials Human-body model Stress (mechanics) Reliability (semiconductor) chemistry CMOS Charged-device model Electronic engineering Optoelectronics Electrical and Electronic Engineering Safety Risk Reliability and Quality business |
| Zdroj: | Microelectronics Reliability. 49:1107-1110 |
| ISSN: | 0026-2714 |
| DOI: | 10.1016/j.microrel.2009.07.039 |
| Popis: | The main purpose of this article is to present some silicon signatures induced by electro-static discharge (ESD) stresses and to propose to approach it with 2D and 3D TCAD simulations and under simplifying assumptions. All test chips are stressed by Human Body Model (HBM), Machine Model (MM) and Charged Device Model (CDM). Moreover each stress is performed on one chip only to avoid cumulative silicon signatures. It appears that the substrate current induced by any of these stresses leads to the same damage on silicon. Thus, HBM, MM and CDM have a common failure and silicon signature. Moreover the information of the Failure Analysis (FA) only cannot provide an exclusive conclusion in term of ESD stress. Also this kind of local stress can be considered as a latent default for the ESD reliability of devices by oxide overstress and/or charge trapping and/or contact impact and/or STI impact. |
| Databáze: | OpenAIRE |
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