14nm FinFET technology SRAM cell margin evaluation and analysis by local layout effect
| Autor: | David Burnett, C. Jerome, K. J. Lee, J. G. Lee, W. Hong, Kwan-Yong Lim, D. K. Sohn, S. Y. Mun, H. C. Lo, Y. J. Shi, O. Hu, J. Versaggi, Sanjay Parihar, S. B. Samavedam |
|---|---|
| Rok vydání: | 2017 |
| Předmět: |
010302 applied physics
Materials science Sram cell 02 engineering and technology 021001 nanoscience & nanotechnology 01 natural sciences Planar CMOS Margin (machine learning) 0103 physical sciences Electronic engineering Node (circuits) Static random-access memory Enhanced Data Rates for GSM Evolution 0210 nano-technology Metal gate |
| Zdroj: | 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S). |
| Popis: | 14nm node SRAM using FinFETs with advanced Replacement Metal Gate (RMG) module shows sensitive Access Distuib Margin (ADM) response to Local Layout Effect (LLE) as seen in planar CMOS technology using RMG [1]. Additionally, 14nm FinFET technology has more LLEs than ever due to the layout variety or tighter minimum design rule applied [2]. Fluorine with very high reaction energy diffuses from WL CONT to Pass Gate (PG) is found to lower PG Vtsat degrading s-ratio and ADM. And, the STI stress from strap cell reduces the SRAM NFET Vtsat of the cell at the array edge degrading ADM. The natural variation of Gate-cut to PG degrades the Vth mismatch resulting in ADM degradation also. These three kinds of LLE and their impacts on ADM are discussed and analyzed in detail in this paper along with mechanisms that can cause the LLEs. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|