A Built-In Self Test Compensating Process-Voltage Variation in Data Paths of High Performance DRAMs
| Autor: | Juseop Park, Kee-Won Kwon |
|---|---|
| Rok vydání: | 2018 |
| Předmět: |
Read-only memory
0209 industrial biotechnology Computer science 020208 electrical & electronic engineering Process (computing) 02 engineering and technology Chip Signal Compensation (engineering) 020901 industrial engineering & automation Reliability (semiconductor) Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Electronic engineering Dram Voltage |
| Zdroj: | 2018 IEEE International Memory Workshop (IMW). |
| DOI: | 10.1109/imw.2018.8388779 |
| Popis: | The efficient built-in self test scheme is proposed for dynamic random-access memory to compensate process and voltage variation. The time-to-digital converter detects the relative process and voltage variation and compensation is proceeded with an adjustable delay with read only memory which is embedded in the chip. It reduces the burden of test time and improves both speed and reliability. Under the data path of a normal read operation with the 20-nm class 8Gb DDR4 DRAM, the effect of process and voltage variation mitigated and lead to a decrease of 0.79 ns in the data access time and an increase of 0.18% in the yield. The proposed scheme alleviates the signal conflict from inter-chip process and voltage difference at 3-D stacked DRAM with through-silicon vias (TSVs). |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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