A 7-bit, 1.4 GS/s ADC With Offset Drift Suppression Techniques for One-Time Calibration
| Autor: | Takahiro Miki, Yuji Nakajima, Akemi Sakaguchi, Norihito Kato, Toshio Ohkido |
|---|---|
| Rok vydání: | 2013 |
| Předmět: |
Engineering
Offset (computer science) Comparator Preamplifier business.industry Electrical engineering Hardware_PERFORMANCEANDRELIABILITY Environmental variation CMOS Robustness (computer science) Hardware_INTEGRATEDCIRCUITS Electronic engineering Calibration algorithm Hardware_ARITHMETICANDLOGICSTRUCTURES Electrical and Electronic Engineering business |
| Zdroj: | IEEE Transactions on Circuits and Systems I: Regular Papers. 60:1979-1990 |
| ISSN: | 1558-0806 1549-8328 |
| DOI: | 10.1109/tcsi.2013.2256236 |
| Popis: | This paper describes a digitally calibrated 7-bit, 1.4 GS/s flash analog-to-digital converter (ADC) implemented in 45-nm CMOS. The proposed offset drift suppression techniques for dynamic comparator and preamplifier make the ADC robust against environmental variation. As a result, once the ADC is calibrated at power up, no more calibration is necessary, even under VDD or temperature variations. The robustness is theoretically and experimentally verified. A calibration algorithm for doubling the ADC accuracy is also presented. The ADC occupies a small area of 0.085 mm2 and dissipates 33.24 mW at 1.4 GS/s from a 1.15 V supply. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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