(Invited) CMP Challenges toward DRAM Device below 20nm Technology
| Autor: | Ji Min Lim, Dong Woo Kim, Sung Ki Park, Kee Joon Oh, Hyung Hwan Kim |
|---|---|
| Rok vydání: | 2014 |
| Předmět: | |
| Zdroj: | ECS Transactions. 60:607-612 |
| ISSN: | 1938-6737 1938-5862 |
| DOI: | 10.1149/06001.0607ecst |
| Popis: | Below 30nm DRAM device technology, we currently have been facing so many challenges such as chip size reduction, particle size reduction, cost reduction and process step reduction. As chip size gets smaller and smaller, manufacturing processes would be very difficult due to particles and affecting defects. Relating to these, some aspects of the chemical mechanical polishing (CMP) processes we are currently challenging were studied case by case. We approached three kinds of techniques toward below 20nm technology. Scratch reduction techniques were reviewed and extreme edge control method by new head tool was introduced and finally nano-colloidal slurry was successfully evaluated for next devices. We would like to emphasize that most important thing is to cooperate with world-wide suppliers and work hand in hand with our chip makers to overcome challenges below 20nm technology. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|